A Loop—Based Apparatus for At—Speed Self

摘要 At-speedtestingusingexternaltesterrequiresanexpensiveequipment,thusbuilt-inself-test(BIST)isanalternativetechniqueduetoitsabilitytoperformon-chipat-speedself-testing.ThemainissueinBISTforat-speedtestingistoobtainhighdelayfaultcoveragewithalowhardwareoverhead.Thispaperpresentsanimprovedloop-basedBISTscheme,inwhichaconfigurableMISR(multiple-inputsignatureregister)isusedtogeneratetest-pairsequences.ThestructureandoperationmodesoftheBISTschemearedescribed.Thetopologicalpropertiesofthestate-transition-graphoftheproposedBISTschemeareanalyzed.Basedonit,anapproachtodesignandefficientlyimplementtheproposedBISTschemeisdeveloped.ExperimentalresultsonacademicbenchmarkcircuitsarepresentedtodemonstratetheeffectivenessoftheproposedBISTschemeaswellasthedesignapproach.

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A Loop—Based Apparatus for At—Speed Self—Testing

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A Loop—Based Apparatus for At—Speed Self—Testing

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